Exciting opportunity for a Design Verification Engineer to join a fast-growing multinational based in Cork.  You will need to have experience in design, testing and verification in hardware and software on SoCs and SoC methodologies for verifying complex units on SoC using industry standard tools and technologies.

Qualifications and Experience:

· Proficient in developing unit and SoC level test benches using OVM/UVM

· Constrained random functional verification environment in System Verilog

· Experience in Gate Level Simulation (GLS) verification flow for SoC verification.

· Experience of pre and post-silicon verification test flow and automated test benches

· Strong knowledge of test-plan generation, coverage analysis transaction level modelling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog

· Verilog, C/C++, System C, Java, TCL/Perl/shell-scripting required

· Building and leading verification teams is a plus

· RTL design and front-end design flow experience

· Excellent communication skills

Educational Requirements:

Min: Bachelor's, Electrical Engineering.
Preferred: Master's, Electrical Engineering.