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Physical Design Engineer

at Clon Recruit (view profile)
Location Cork, Ireland
Date Posted June 28, 2018
Category Technical and Engineering
Job Type Permanent (Full-time)
Salary Range Not Disclosed

Description

You will be part of a new team that will drive and execute on all phases of the complete physical design flow for MSM/MDM/CSMs at the core and chip-level in 28nm, 20nm and 14nm CMOS technology.

RESPONSIBILITIES:

· You will be part of a world-wide team responsible for the complete Physical Design Flow for MSM/MDM/CSM chips.

· Work on the physical design execution and integration of the IP into the SoC.

· Manage schedules, plans, status, risks and support cross-functional engineering effort

· Work with the RTL design teams on understanding design in context of physical design timing closure including developing of timing constraints required for implementation.

· Work with the DFT team on understand DFT design in regards to physical design timing closure.

· Enablement of low power implementation methods

· Developing new scripts/flows to improve the PD flow.

Minimum Qualifications, skills, experience:

· Experience and knowledge of tools for physical design implementation in advanced technologies like 28nm, 20nm and 14nm CMOS.

· Knowledge of entire PD flow from netlist to GDS (Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Post route optimization and DRC closure).

· Understanding of Floorplanning, Placement, CTS, P&R

· Experience in partitioning, pins assignment, time budgeting and feedthroughs.

· Experience using different techniques for low power designs and UPF/CPF flows.

· Good understanding of Primetime STA tool and timing closure methodologies.

· Developing and implementing timing ECOs including effect on congestion/routing/power.

· Understanding of power grid, clock tree, and low-power reduction implementation methods.

· Understanding of signal integrity and timing closure issues such as OCV/AOCV/Statistical Timing.

· Understanding of Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification

· Expert in automation skills using Perl and tcl and able to develop/support flows related to floorplanning, integration and design validation.

· Good communication skills and ability & desire to work in a cross-functional team environment.

Education Requirements
Required: Bachelors in Engineering
Preferred: Masters Degree in Engineering a plus